How D-Wave processors are built, and how they use the physics of spin systems to implement quantum computation
Aim, audience and required background
The aim of this document is to describe how a quantum computer is physically built, how quantum bits and their associated circuitry are created, addressed, and controlled, and what is happening inside the computer when programmers send information to a D-Wave quantum machine.
The material here is written using very high level concepts and is designed to be accessible to both technical and non-technical audiences. Some background in physics, mathematics and programming is useful to help understand the concepts presented in this document, although this is not a solid requirement. In order to understand the material here you may also wish to read the Quantum Computing Primer document first.
What you will learn
By following through the material in this primer, you will learn:
SECTION 1: Inside the processor
1.1 - The building blocks of QC
In the previous tutorial, our representation of qubits as bits of information has been in a symbolic way, 0, 1 and a superposition state of both 0 and 1. But how are the qubits physically made? What do they look like?
Classical CMOS transistors
The way that we encode and access information in modern digital computers is by adjusting and monitoring voltages that are present on tiny transistor switches inside integrated circuits. Each transistor is addressed by a bus which is able to set it to a state of either 0 (a low voltage) or 1 (a high voltage). So we use the idea of an electrical voltage to 'encode' bits of information in a physical device.
The SQUID - a quantum transistor
Quantum computers have similarities to and differences from this CMOS transistor idea. Figure 1 shows a schematic illustration of what is known as a superconducting qubit (also called a SQUID), which is the basic building block of a quantum computer (a quantum 'transistor', if you like). The name SQUID comes from the phrase Superconducting QUantum Interference Device. The term 'Interference' refers to the electrons - which behave as waves inside a quantum waves, interference patterns which give rise to the quantum effects. The reason that quantum effects such as electron waves are supported in such a structure - allowing it to behave as a qubit - is due to the properties of the material from which it is made. The large loop in the diagram is made from a metal called niobium (in contrast to conventional transistors which are mostly made from silicon). When this metal is cooled down, it becomes what is known as a superconductor, and it starts to exhibit quantum mechanical effects.
A regular transistor allows you to encode 2 different states (using voltages). The superconducting qubit structure instead encodes 2 states as tiny magnetic fields, which either point up or down. We call these states +1 and -1, and they correspond to the two states that the qubit can 'choose' between. Using the quantum mechanics that is accessible with these structures, we can control this object so that we can put the qubit into a superposition of these two states as described earlier. So by adjusting a control knob on the quantum computer, you can put all the qubits into a superposition state where it hasn't yet decided which of those +1, -1 states to be.
Figure 1. Schematic of a superconducting qubit, the basic building block of the D-Wave OneTM
Quantum Computer. The arrows indicate the magnetic spin states which encode the bits of information as +1 and -1
values. Unlike regular bits of information, these states can be put into quantum mechanical superposition.
1.2 - A fabric of programmable elements
In order to go from a single qubit to a multi-qubit processor, the qubits must be connected together such that they can exchange information. This is achieved through the use of elements known as couplers. The couplers are also made from superconducting loops. By putting many such elements (qubits and couplers) together, we can start to build up a fabric of quantum devices that are programmable. Figure 2 shows a schematic of 8 connected qubits. The loop shown in the previous diagram has now been stretched out to form one of the long gold rectangles. At the points where the rectangles cross, the couplers have been shown schematically as blue dots.
Figure 2. Left: A schematic illustration of 8 qubit loops (gold). The blue dots are the locations of the 16 coupling elements that allow the qubits to exchange information. Mathematically, these elements couple together variables in a problem that you wish the computer to solve.
1.3 - Support circuitry: Addressing, programming and reading the qubits
There are several additional components necessary for processor operation. A large part of the circuitry that surrounds the qubits and couplers is a framework of switches (also formed from Josephson junctions) forming circuitry which both addresses each qubit (routes pulses of magnetic information to the correct places on chip) and stores that information in a magnetic memory element local to each device. The majority of the 25,000 Josephson junctions in a Rainier processor are used to make up this circuitry. Additionally, there are readout devices attached to each qubit. During the computation these devices are inactive and do not affect the qubits' behaviour. After the computation has finished, and the qubits have settled into their final (classical) 0 or 1 states, the readouts are used to query the value held by each qubit and return the answer as a bit string of 0's and 1's to the end user. Here is a video showing how some of the processor elements are combined to produce the computational fabric at the core of the D-Wave OneTM Rainier processor:
Inside the chip: Video showing 3D Animation of how the components in a Rainier processor fit together
The image in figure 3 shows the layout of the actual circuit, as drawn in a CAD program by a D-Wave circuit layout designer, and is ready to be sent off to the processor fabrication foundry. Here the full complexity of the processor is revealed. In this image, the qubits are now shown as long pink strips, which have been stretched out even more than in the previous figure. The green and yellow elements that sit in the spaces between qubits are components which make up the programmable circuitry mentioned above. The yellow dots are Josephson junctions embedded within this circuitry.
Figure 3. (Click to open a larger version in a new tab) False-colour view of part of a CAD layout of the
Rainier chip architecture. This image is from a real processor design layout file, which is sent to the manufacturer and
from which the processors are fabricated layer by layer. The long qubit loops are now shown as the pink areas, the control
circuitry lines which carry currents to the programmable are indicated by the green features and the Josephson junctions are shown in yellow.
Note that this architecture is very different from conventional computing. The processor has no large areas of memory (cache), rather each qubit has a tiny piece of memory of its own. In fact, the chip is architected more like a biological brain than the common 'Von Neumann' architecture of a conventional silicon processor. One can think of the qubits as being like neurons, and the couplers as being like synapses that control the flow of information between those neurons. We'll see in later programming tutorials how this 'brain-like' architecture helps us to solve problems in machine learning and artificial intelligence using quantum computers.
1.4 - Manufacturing quantum processors
Figure 4 shows an image of the final chips after fabrication in a superconducting electronics foundry. The chips are 'stamped' onto a silicon wafer using techniques modified from the processes used to make semiconductor integrated circuits. There are several processors visible on this wafer image. The largest, near the bottom center, has 128 qubits connected together with 352 connection elements between them. The qubit/coupler circuits on each individual processor are the cross-hatched looking patches visible in this image. This is known as a Rainier processor and it is the type of processor found inside the D-Wave One.
Figure 4. Photograph of a wafer of Rainier processors, including the 128-qubit processor used in the D-Wave OneTM QC system.
It is important to try and use as much knowledge from the semiconductor industry as possible when fabricating large-scale integrated circuits, as through decades of testing, good parameters have been found to make integrated circuit yields good enough for the processors to be used commercially.
The techniques learned from the semiconductor industry have resulted in the construction of a Large-Scale Integration (LSI) fabrication capability owned by D-Wave in Santa Clara, USA (2006 - present). This fabrication capability is unique. Shown in Figure 5 is a cross section of one of the processors fabricated at D-Wave's superconducting electronics foundry. The fabrication process that has been developed is able to yield LSI (50,000+ Josephson junctions for Vesuvius) superconducting circuits. It is the only superconducting fabrication facility capable of yielding superconducting processors of this complexity. Fabrication yield is critical to improving processor performance and requires on-going significant investment, and in order to maintain historical qubit doubling rates, investments are being made to improve the capability into VLSI (1,000,000+ Josephson junction per processor) territory over the next five years.
Figure 5. A microscope cross-section of a D-Wave processor, fabricated using a 6-metal wiring layer process. The layer which is used to form the Josephson junctions is shown near the bottom of this sandwich structure.
SECTION 2: Outside the processor
2.1 - The processor packaging
To build the quantum computer, one of these chips is selected from the wafer, and placed in the center of the processor packaging system, as shown in Figure 6. This image shows the chip area open, just after it has been wire bonded to connect it to the signal lines. It is possible to see the signal lines on the surrounding printed circuit board. There are far fewer incoming lines than there are programmable elements on the processor, which is made possible by additional circuitry - in the form of demultiplexers and signal routing and addressing - all implemented in superconducting logic circuitry on the chip.
Figure 6. A photograph of the chip after being bonded to the circuit board which allows signals lines to be connected.
2.2 - Computer cooling
Reduction of the temperature of the computing environment below approximately 80mK is required for the processor to function, and generally performance increases as temperature is lowered - the lower the temperature, the better. 20mK is targeted as the lowest temperature that can be easily reached as an operating point. The processor and parts of the input/output (I/O) system, comprising roughly 10kg of material, must be cooled to these temperatures. Most of the physical volume of the current system is due to the large size of the refrigeration system. The refrigeration system used to cool the processors is known as a dilution refrigerator.
The inset in Figure 7 shows the chip packaging attached to the cooling apparatus. Note that the area around the chip has now been closed up to protect it from being damaged. When the computer is being operated, this part is sealed inside a vacuum chamber Because quantum processors require low temperatures for the quantum effects to be sustained, the entire piece shown in the inset of figure 7 is cooled to around 20mK, which is approximately 100 times colder than interstellar space.
To reach the near-absolute zero temperatures at which the system operates, the refrigerators use liquid Helium as a coolant. The type of refrigerator inside the D-Wave OneTM system is known as a "dry" dilution refrigerator. This means that all the liquid helium resides inside a closed cycle system, where it is recycled and recondensed using a pulse-tube technology. This makes them are suited to remote deployment, as there is no requirement for liquid helium replenishment on-site.
The specialized equipment to allow cooling to these temperatures is available commercially and runs reliably. The refrigeration technology is also mature enough that the system has a turnkey operation. The computer can be cooled down to operating temperature within several hours, and once this temperature is reached remain cold for months or years.
Figure 7. (Click to view large version in new window) Schematic of the inside of the quantum computing system
(inside its dedicated room) before the shielding and vacuum containers are attached. The chip packaging is housed
inside the silver cylinder at the bottom of the assembly, as shown opened up in the insert.
2.3 - Computer shielding and wiring
The I/O subsystem is responsible for passing information from the user to the processor and back. The signals are low frequency (<30MHz) analog currents, carried on metal lines, transitioning to superconducting lines at low temperatures. Key components of the I/O subsystem include the processor mount and wirebonding to it; low frequency bandpass filters for removing noise from the lines; room temperature electronics for converting signals coming from a front end server to analog currents; and the front end server which receives programming instructions from a user.
Nearly all aspects of the I/O subsystem are designed, manufactured, and tested by D-Wave in their Burnaby facility. Many of the specifications of the I/O system place unusual demands on the materials and processes involved. For example, much of the I/O subsystem must function at 20mK and be robust against multiple warming / cooling cycles between room temperature and base. Much of the subsystem must be made using superconducting metals, such as tin, which are typically non-standard for manufacturers. Additionally none of the materials close to the processor can be magnetic. To enforce this requirement, the company individually tests the magnetic character of every single component of each I/O subsystem at base temperature, and includes only those components that pass.
The current I/O subsystems provide 192 heavily filtered lines from room temperature to the processor, and are designed for optimal operation of a single 512-qubit Vesuvius processor. The D-Wave processor design is adversely affected by stray magnetic fields, and extreme care must be taken to exclude these. The current magnetic shielding system achieves fields less than 1 nanoTesla (nT) in three dimensions across the entire volume of the processor. This is achieved by a system comprising five concentric cylindrical shields, some of them high permeability metals and some of them superconducting. Integrated, on the processors, are magnetic sensors that measure the ambient field. Countering magnetic fields are applied that zero the field at these sensors. The temperature of the assembly is then slowly reduced, and the superconducting shields go superconducting, and 'lock' the zeroed field in place.
2.4 - Computer form factor
In addition to the magnetic shielding, the system sits inside a shielded room which screens out RF electromagnetic noise. The only path for signals between the inside and outside of the shielded room is a digital optical channel carrying programming information in, and results of computations out.
This shielded room doubles as the housing for the D-Wave OneTM system. Figure 8 shows a photograph of two D-Wave OneTM systems in their final, assembled form. The main black cube measures approximately 10'x10'x10', and there is an auxiliary cabinet where the server and control systems are housed. This footprint of the entire system is fairly large, being comparable in size to modern supercomputers which are housed in datacenter facilities. For this reason, the current mode of use of these systems is as a cloud computing resource.
Figure 8. Left: Photograph of two D-Wave OneTM Systems being tested in the lab.
The large black cube unit houses the refrigerated and shielded quantum computing system, whilst the adjoining cabinet
contains the control racks for the unit and the server for remote connection to the system.
2.5 - Cloud based access
The way that the quantum processors are programmed is using a cloud-based model. This means that the systems can be programmed remotely from any location with an internet connection. Figure 9 shows an overview of how a user interacts with the system. Each D-Wave OneTM system has its own server. The system server handles the job queuing and scheduling, so that multiple users can access the system simultaneously. As more systems are brought online, this model will transition to the quantum processing ability being a co-processing resource that is accessible through (and used in conjuction with) classical cloud computing methods.
For more information on programming the system and the software side of quantum computing, please also read the QC software document, which follows on from this hardware overview.
Figure 9. Schematic of the system infrastructure and connection to LAN/internet
3.1 - The future of the hardware
For the past 8 years, the number of qubits on D-Wave's processors has been steadily doubling each year (see figure 10). This trend is expected to continue. To create processors with numbers of qubits up to around 10,000, the current fabrication process can simply be scaled to add more qubits in the same way that they are arranged currently. To go beyond ten-thousand into hundreds of thousands or millions of qubits will require major processor redesign, but there are certainly ways in which this can be achieved and it is not seen as a fundamental obstacle to improving the hardware.
Figure 10. 'Rose's law' for quantum computing mimics the conventional 'Moore's law' paradigm
seen in semiconductor processor development
In addition to doubling the qubit count every 12 months, further improvements are planned, which include increasing the precision of the programmable elements, reducing the footprint of the entire system, reducing the energy consumption of the system, and the inclusion of parallel cores (i.e. multiple processors) within a single refrigeration unit.